Microelectronic assemblies are formed by attaching an integrated circuit component, such as an integrated circuit die, to a substrate, such as a printed circuit board, by solder bump interconnections. This "flip-chip" method is accomplished by superposing solder bumps deposited onto bond pads of the integrated circuit component so that the solder bumps rest against bond pads on the substrate. This preassembly is then heated to reflow the solder. In the product assembly, the component is spaced apart from the substrate by a gap. The solder bump interconnections extend across the gap to physically attach the component to the substrate and electrically connect electrical features on the component to a circuit trace on the substrate to transmit signals to and from the component for processing.
During reflow, the solder bumps collapse. This collapse is a result of the liquefaction of the solder alloy upon heating above the melting temperature of the solder alloy. This collapse leads to a reduced gap between the component and the substrate, and also leads to the solder bumps having an increased width and a decreased height. As the solder liquefies, the component collapses toward the substrate, and a solder bump interconnection is formed in a typically rounded shape, due to surface tension of the solder. When the collapse of the component is relatively large, the increase in width of the solder joints can lead to shorts between adjacent solder joints.
In addition, the collapse of the solder bumps during reflow leads to a decrease in the standoff. Flip-chip assemblies typically require an underfilling encapsulant, such as a filled epoxy formulation, to provide stress relief to the assembly and the solder bump interconnections. The precursor of the underfilling encapsulant is typically deposited adjacent to the attached component and drawn into the gap via capillary action. As the gap height decreases, difficulties can arise in drawing the encapsulant into the gap.
Consequently, a need exists for a microelectronic assembly having predetermined standoff between the component and the substrate and controlled lateral dimensions between interconnections to avoid shorting.